/* $Id$ */
/* vim: set filetype=verilog ts=8 sw=4 tw=132: */
/*****************************************************************************
 
              (c) Copyright 1987 - 2012,  VIA Technologies, Inc.       
                            ALL RIGHTS RESERVED                            
                                                                     
 This design and all of its related documentation constitutes valuable and
 confidential property of VIA Technologies, Inc.  No part of it may be
 reproduced in any form or by any means   used to make any transformation
 / adaptation / redistribution without the prior written permission from the
 copyright holders. 
 
------------------------------------------------------------------------------

  DESCRIPTION:

  FEATURES:

  TODO:

  AUTHORS:
     Shawn Fang
    
------------------------------------------------------------------------------
                             REVISION HISTORY
    $Log$

*****************************************************************************/
module execute(     
	/*
	// Outputs
                     output [31:0] valE,//              (valE[31:0]),
                     output cnd,//               (cnd),
                     // Inputs
                     input  clock,//             (clock),
                     input  reset,//             (reset),
                     input  [3:0] icode,//             (icode[3:0]),
                     input  [3:0] ifun,//              (ifun[3:0]),
                     input  [31:0] valC,//              (valC[31:0]),
                     input  [31:0] valB, //             (valB[31:0]),
                     input  [31:0] valA
		 */
		 // Outputs
                     output [3:0] e_icode,         //  (e_icode[31:0]),
                     output [3:0] e_ifun ,        //   (e_ifun[31:0]),
                     output [31:0] e_valE ,         //  (e_valE[31:0]),
                     output [31:0] e_valA ,       //    (e_valA[31:0]),
                     output [3:0] e_dstE ,       //    (e_dstE[3:0]),
                     output [3:0] e_dstM ,    //       (e_dstM[3:0]),
                     output e_cnd      ,     //  (e_cnd),
                     output reg[2:0] e_stat,       //     (e_stat[3:0]),
                     // Inputs
                     input  clock      ,//        (clock),
                     input  reset      ,//        (reset),
                     input  [3:0] d_icode   ,//         (d_icode[3:0]),
                     input  [3:0] d_ifun    ,//         (d_ifun[3:0]),
                     input  [2:0] d_stat    ,//         
                     input  [3:0] d_dstE   ,//          (d_dstE[3:0]),
                     input  [3:0] d_dstM    ,//         (d_dstM[3:0]),
                     input [31:0]  d_valC  ,// ,//           (d_valC[31:0]),
                     input  [31:0] d_valB   ,//         (d_valB[31:0]),
                     input  [31:0] d_valA   ,//         (d_valA[31:0])
		     input  [2:0] m_stat,
		     input  [2:0] w_stat,
		     input  E_stall,
		     input  E_bubble
		);//              (valA[31:0]));


always @ (posedge clock or posedge reset)
    begin
	if(reset)
	    e_stat<=`SAOK;
	else
	begin
	    if(E_stall)
		e_stat<=e_stat;
	    else if(E_bubble)
		e_stat<=`SAOK;
	    else
		e_stat<=d_stat;
	end
    end

wire   [31:0] e_valB,e_valC;		
wire   setcc;
wire   [2:0] alucc;
wire   [2:0] cc;
wire   [3:0] e_dstE_o;
assign e_dstE=(e_icode==`IRRMOVL && ~e_cnd)?`RNUL:e_dstE_o;
alu U_alu(//output
	.e_valE(e_valE),
	.e_setcc(setcc),
	.e_alucc(alucc),
	//input
	.E_icode(e_icode),
	.E_ifun(e_ifun),
	.E_valC(e_valC),
	.E_valB(e_valB),
	.E_valA(e_valA),
	.m_stat(m_stat),
	.w_stat(w_stat)
    );

cond U_cond(
	//output
	.e_cnd(e_cnd),
	//input
	.E_ifun(e_ifun),
	.e_cc(cc));
regCC U_regCC
	(//output
	.e_cc(cc),
	//input
	.clock(clock),
	.reset(reset),
	.e_alucc(alucc),
	.e_setcc(setcc));
		 
ppregs_E U_ppregs_E
    (
	.clock(clock),
	.reset(reset),
	.E_stall(E_stall),
        .E_bubble(E_bubble),
	.icode_i(d_icode),
	.ifun_i(d_ifun),
	.dstE_i(d_dstE),
	.dstM_i(d_dstM),
	.valC_i(d_valC),
	.valA_i(d_valA),
	.valB_i(d_valB),

	.icode_o(e_icode),
	.ifun_o(e_ifun),
	.dstE_o(e_dstE_o),
	.dstM_o(e_dstM),
	.valC_o(e_valC),
	.valA_o(e_valA),
	.valB_o(e_valB)
	    );		 
endmodule
